edi2kg464128v 4 megabyte synchronous card edge dimm 1 edi2kg464128v rev. 0 3/98 eco#9977 the edi2kg64128vxxd is a synchronous sram, 60 position card edge dimm (120 contacts) module, orga- nized as 4x128kx64. the module contains eight (8) synchronous burst ram devices, packaged in the in- dustry standard jedec 14mmx20mm tqfp placed on a multilayer fr4 substrate. the module architecture is defined as a synchronous only, flow-through, early write device. this module provides high performance, ultra fast access times at a cost per bit benefit over bicmos asynchronous sram based devices. as well as improved cost per bit, the use of synchronous or synchronous burst devices or modules can ease the memory subsystem design by reducing or easing the memory controller requirement. synchronous operations are in relation to an externally supplied clock, registered address, registered global write, registered enables as well as an asynchronous output enable. all read and write operations to this module are performed on quad words (64 bit opera- tions). write cycles are internally self timed and are initiated by a rising clock edge. this feature relieves the designer the task of developing external write pulse width circuitry. ? 4x128kx64 synchronous ? flow-through architecture ? clock controlled registered bank enables (e1\, e2\, e3, e4\) ? clock controlled registered address ? clock controlled registered global write (gw\) ? aysnchronous output enable (g\) ? internally self-timed write ? module sleep mode enable (zz) ? gold lead finish ? 3.3v + 10% operation ? access speed(s): tkhqv=9.5, 10, 11, 12, 15ns ? common data i/o ? high capacitance (30pf) drive, at rated access speed ? single total array clock ? multiple vcc and gnd advanced module features dq0-dq63 input/output bus a0-a15 address bus e1\, e2\, e3\, e4\ synchronous bank enables clk array clock gw\ synchronous global write enable g\ asynchronous output enable zz module sleep enable vcc 3.3v power supply vss gnd pin names electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? http://www.electronic-designs.com 4x128kx64, 3.3v synchronous flow-through
edi2kg464128v 4 megabyte synchronous card edge dimm 2 edi2kg464128v rev. 0 3/98 eco#9977 pin configuration functional block diagram g\ gw\ e1\ gw\ g\ e\ dq zz gw\ g\ e\ dq zz gw\ g\ e\ dq zz gw\ g\ e\ dq zz e3\ gw\ g\ e\ dq zz gw\ g\ e\ dq zz gw\ g\ e\ dq zz gw\ g\ e\ dq zz e2\ e4\ zz clk clk clk clk clk clk clk clk clk a0-a16 128kx64 128kx64 128kx64 128kx64 128kx64 128kx64 128kx64 128kx64 dq0-dq63 vss vss a0 a1 a15 a2 a14 a3 a13 vcc vcc a4 a12 a5 a6 a7 vss a8 vss clk vss e4\ vcc e3\ g\ vss dq0 dq1 dq2 dq3 vcc dq8 dq9 dq10 dq16 dq17 dq18 dq19 vcc dq24 dq25 dq26 dq27 vss dq32 dq33 dq34 dq35 vcc dq40 dq41 dq42 dq43 vss dq48 dq49 dq50 dq51 vcc dq56 dq57 dq58 dq59 vss vss dq11 a11 a10 a9 vss rfu vss zz vss e2\ vcc e1\ gw\ vss dq7 dq6 dq5 dq4 vcc dq15 dq14 dq13 dq12 vss dq23 dq22 dq21 dq20 vcc dq31 dq30 dq29 dq28 vss dq39 dq38 dq37 dq36 vcc dq47 dq46 dq45 dq44 vss dq55 dq54 dq53 dq52 vcc dq63 dq62 dq61 dq60 vss a16 11 13 15 17 19 21 23 25 27 28 26 24 22 20 18 16 14 12 10 29 31 33 35 37 39 41 43 45 47 49 51 52 50 48 46 44 42 40 38 36 34 30 32 53 55 57 59 61 63 65 67 69 71 73 54 56 58 60 62 64 66 68 70 72 74 75 77 79 81 83 85 87 89 91 93 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 95 97 99 101 103 105 107 109 111 113 115 117 119 118 120 3 5 7 9 1 8 6 4 2
edi2kg464128v 4 megabyte synchronous card edge dimm 3 edi2kg464128v rev. 0 3/98 eco#9977 *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. absolute maximum ratings* voltage on vcc relative to vss -0.5v to +4.6v vin -0.5v to vcc +0.5v storage temperature -55c to +125c operating temperature (commercial) 0c to +70c operating temperature (industrial) -40c to +85c short circuit output current 10 ma synchronous only - truth table operation e1\ e2\ e3\ e4\ gw\ g\ zz clk dq synchronous write-bank 1 l h h h l h l high-z synchronous read-bank 1 l h h h h l l synchronous write-bank 2 h l h h l h l high-z synchronous read-bank 2 h l h h h l l synchronous write-bank 3 h h l h l h l high-z synchronous read-bank 3 h h l h h l l synchronous write-bank 4 h h h l l h l high-z synchronous read-bank 4 h h h l h l l snooze mode x x x x x x h x high-z pin descriptions dimm pins symbol type description 3, 5, 7, 9, 15, 17, a0-a16 input addresses: these inputs are registered and must meet the setup and hold 1 9, 23, 20, 18, 16, synchronous times around the rising edge of clk. the burst counter generates internal 14, 10, 8, 6, 4 addresses associated with a0 and a1, during burst and wait cycle. 38 gw\ input global write: this active low input allows a full 72-bit write to occur synchronous independent of the bwe\ and bwx\ lines and must meet the setup and hold times around the rising edge of clk. 27 clk input clock: this signal registers the addresses, data, chip enables, write control synchronous and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clocks rising edge. 36, 32, e1\, e2\ input bank enables: these active low inputs are used to enable each individual 35, 31 e3\, e4\ synchronous bank and to gate adsp\. 37 g\ input output enable: this active low asynchronous input enables the data output drivers. zz input module snooze: this active high signal places the memory module in sleep asynchronous mode (low power consumption). various dq0-63 input/output data inputs/outputs: first byte is dq0-7, second byte is dq8-15, third byte is dq16-23, fourth byte is dq24-31, fifth byte is dq32-39, sixth byte is dq40-47, seventh byte is dq48-55 and the eight byte is dq56-64. various vcc supply core power supply: +3.3v -5%/+10% various vss ground ground
edi2kg464128v 4 megabyte synchronous card edge dimm 4 edi2kg464128v rev. 0 3/98 eco#9977 max description sym typ 9.5 10 11 12 15 units power supply current icc1 1.55 2.8 2.2 2.2 2.7 2.0 a power supply current icc .750 1.8 1.5 1.3 1.3 1.0 a device selected,no operation snooze mode icczz 200 300 300 300 300 300 ma cmos standby icc3 400 500 500 500 500 500 ma clock running-deselect icck 600 900 900 900 900 900 ma dc electrical characteristics - read cycle parameter sym min typ max units supply voltage vcc 3.14 3.3 3.6 v supply voltage vss 0.0 0.0 0.0 v input high vih 1.1 3.0 vcc+0.3 v input low vil -0.3 0.0 0.3 v input leakage ili -2 1 2 m a output leakage ilo -2 1 2 m a recommended dc operating conditions ac test conditions input pulse levels vss to 3.0v input and output timing ref. 1.25v output test equivalencies ac test load dq z 0 = 50 w fig. 1 output load equivalent vt = 1.25v 50 w 9.5ns 10ns 11ns 12ns 15ns description sym min max min max min max min max min max units clock cycle time tkhkh * * 12 13 15 20 ns clock high time tkhkl * * 5556ns clock low time tklkh * * 5556ns clock to output valid tkhqv * * 10 11 12 15 ns clock to output invalid tkhqx1 * * 3333ns clock to output low-z tkhqx * * 2222ns output enable to output valid tglqv * * 4556ns output enable to output low-z tglqx * * 0000ns output enable to output high-z tghqz * * 4555ns address setup tavkh * * 2.5 2.5 2.5 2.5 ns bank enable setup tevkh * * 2.5 2.5 2.5 2.5 ns address hold tkhax * * 1.0 1.0 1.0 1.0 ns bank enable hold tkhex * * 1.0 1.0 1.0 1.0 ns read cycle timing parameters *tbd
edi2kg464128v 4 megabyte synchronous card edge dimm 5 edi2kg464128v rev. 0 3/98 eco#9977 9.5ns 10ns 11ns 12ns 15ns description sym min max min max min max min max min max units clock cycle time tkhkh * * 12 13 15 20 ns clock high time tkhkl * * 5 5 5 6 ns clock low time tklkh * * 5 5 5 6 ns address setup tavkh * * 2.5 2.5 2.5 2.5 ns address hold tkhax * * 1.0 1.0 1.0 1.0 ns bank enable setup tevkh * * 2.5 2.5 2.5 2.5 ns bank enable hold tkhex * * 1.0 1.0 1.0 1.0 ns global write enable setup twvkh * * 2.5 2.5 2.5 2.5 ns global write enable hold tkhwx * * 1.0 1.0 1.0 1.0 ns data setup tdvkh * * 2.5 2.5 2.5 2.5 ns data hold tkhdx * * 1.0 1.0 1.0 1.0 ns write cycle timing parameters synchronous read cycle tkhqx dq read cycle q(addr 1) tkhqz gw\ oe\ addr ce\ clk tkhqv addr 1 tkhkh tklkh tkhkl tglqx back to back read q(addr 1) tkhqx1 q(addr 2) tglqv addr 1 tkhax addr 2 tavkh ex\ g\
edi2kg464128v 4 megabyte synchronous card edge dimm 6 edi2kg464128v rev. 0 3/98 eco#9977 sync write cycle tghkh tgwlkh tavkh tdvkh write cycle g\ gw\ addr clk ce\ addr 1 tklkh tkhkh tkhkl back to back writes tkhgh tkhdx tkhgwh addr 1 addr 2 tkhax dq ex\ sync read/write cycle write cycle tdvkh back to back cycles g\ controlled d (addr 2) gw\ dq q(addr 1) read cycle tkhqx tavkh g\ addr ce\ clk tkhqv addr 1 tkhdx addr 2 tkhkh tklkh tkhkl tkhdx
edi2kg464128v 4 megabyte synchronous card edge dimm 7 edi2kg464128v rev. 0 3/98 eco#9977 package description ordering information part number organization voltage speed (ns) package edi2kg464128v95d* 4x128kx64 3.3 9.5 120 card edge dimm edi2kg464128v10d* 4x128kx64 3.3 10 120 card edge dimm edi2kg464128v11d 4x128kx64 3.3 11 120 card edge dimm edi2kg464128v12d 4x128kx64 3.3 12 120 card edge dimm EDI2KG464128V15D* 4x128kx64 3.3 15 120 card edge dimm *consult factory for availability electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? http://www.electronic-designs.com electronic designs inc. reserves the right to change specifications without notice. cage no. 66301 120 lead card edge dimm r1 r4 3.513 max. .041.002 1.250 1.360.003 1.760.002 1.650 .050 typ. .150 .074.003 1.125 max. r.031 .210 max. .200 min. .200 typ. .195 r7 r8 173 r2 r3 r5 r6 r9 r10
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